|WinUAE 4.9.1 beta4 ||[powerzx], 2022-01-15 15:26:30|
[Source: http://eab.abime.net/showthread.php?t=109203&page=4]Beta 4:
- uaegfx overlay was not synced with screen dragging. It still works strangely if screen with overlay is not in front screen because Picasso96 does not yet support overlay fully during screen dragging.
- Reset filter button did not reset manual filter settings.
- Added IDE scsi.device disable option to misc panel list.
- if number of planes changed mid scanline, whole line was drawn using planecount that was active when line started. If plane count was increased mid scanline, line was still drawn using lower plane count. If plane count was lowered, output was correct. (vAmiga test)
- Fixed x86 bridgeboard (AT variants only) boot crash if optimized build. Not sure if it was compiler bug or something else but I found a way to work around it. I think this exact same bug has happened previously.
- A1000 left hblank ends 3 lores pixels later than other models.
Later 4.9.0 beta series introduced bugs:
- If VSYNC starts after vertical wraparound (can happen in programmed modes), lines after wraparound before VSYNC was not drawn.
- HCENTER (ECS Denise only) "blanking" did not work.
- Left side did not open far enough in extreme overscan mode.
- OCS Agnus + OCS Denise: last blanked line bug on top of screen was not visible if line also had bitplane enabled.
- Direct 3D 11 mode shader buffer leak fixed. Caused crash after few dozens or so display mode switches. (4.9.0)
This should fix remaining known 4.9.0 bugs.
- "Manual" BPL1DAT write disabling border timing updated. Also OCS Denise limit was not checked, OCS Denise ignores BPL1DAT writes until hblank end. (OCS Denise: border is forced to enabled state during hblank start to hblank end, ECS Denise/AGA: border is enabled when hblank starts).
- "Manual" BPL1DAT write between hblank start and hsync start: border did not open. Now it does. ECS Denise/AGA only.
- If Remove interlace artifacts is enabled, last border lines now have correct color (border color or black). 4.9.0 had temporary hack that always used black.
- OCS Denise topmost line (Line that is mostly black, except tiny part of border color in right border) had off by one line bug.
- Reset blitter before loading state file. 4.9 new blitter emulation did not reset all registers fully, loading state file on the fly might have caused corruption due to blitter not being fully reset.
- Programmed mode display size calculation modified. 4.4 and earlier used both horizontal sync and horizontal blank to calculate internal width and horizonta position. 4.9.0 used only more accurate way but only used horizontal sync. This caused some modes to be too wide internally (wrong aspect ratio) and/or have horizontal offset. Horizontal blank and sync is again used to calculate width and position if normal overscan mode. Higher overscan modes use only hsync (allows glitch-free emulation of hblank "effects", if something someday does it.. Hblank can be moved without causing display resync.)
- 4.9.0b40 blitter final D update was incomplete, final D is not skipped immediately when BLTSIZE is written to but when apparently blitter when sequencer starts.
- Hardfile images less than 4M are now mounted correctly as hardfiles when drag and dropped if file has common HDF extension (HDF/HDZ/VHD).
- Removed "PAL" filter preset. It has been unsupported since long time ago..
- Epson printer emulation does not anymore print each page as a separate document.
- Added IDE scsi.device disable hack. Removes ROM scsi.device from exec ResModules list, does not modify ROM. UAE boot ROM must be enabled. Config file only scsidevice_disable=true. Disabling is not done if any IDE device is added to A600/A1200/A4000 IDE or indirect ROM mode is enabled. Makes booting noticeably quicker on OS39 and newer KS versions if mainboard IDE is not needed.
If BPL1DAT write disables border and active sprite was hidden behind the border:
- OCS Denise: sprite is visible 1 lores pixel (2 hires) earlier than bitplane first pixel.
- ECS Denise: sprite is visible 2 lores pixels (4 hires) earlier than bitplane first pixel.
- AGA: sprite is visible 1.5 lores pixels (3 hires) earlier than bitplane first pixel. (This requires subpixel mode, without subpixel it becomes 1 lores pixel)
- Adjusted programmed mode size/position calculation.
- Adjusted copper emulation, waits for too large horizontal position woke up normally.
- Delay warp mode automatic key release by few frames, some programs might not like immediate keypress/release pair.
- Windows event processing change fix.
- Border "bug" emulated (ECS Denise and AGA, does not affect OCS Denise). If bitplane DMA (BPL1DAT) happens inside VBLANK, border state gets disabled, when first non-VB line starts, line stripe from HDIW start to first BPL1DAT is still in "not border" state: sprites are visible and borderblank does not affect it. This happens because border state normally gets enabled when HBLANK goes from inactive to active state but it looks like HBLANK does not affect border state inside VBLANK. It can also happen during later scanlines if programmed HBLANK starts too early, before last BPL1DAT access. (HBLANK enables border, BPL1DAT access disables it again).
Quick few days long beta series. JIT bug can be very annoying (it triggering depends on used software) when using emulated RTG boards. I think it is better to release fix before I break chipset emulation again, hopefully this time it only takes few months..
This thread is only for 4.9.0/4.9.1 beta introduced bugs or features. Always test with 4.4.0 and 4.90 first! Problem exists in 4.4.0 or older: do not post in this thread!
4.9.0 bugs fixed:
- JIT indirect safe mode MOVEM.W from memory did nit sign extend registers (very, very old bug but apparently it was almost invisible until now because previously indirect MOVEM was not used unless VRAM was not indirect capable and direct MOVEM was still incorrectly used even when indirect mode was enabled. This was fixed in 4.9.0).
- Really force all emulated gfx board VRAM accesses to use indirect JIT. Previously used method still allowed direct JIT if code first accessed plain RAM and later (after it was translated) same code accessed VRAM. Fixes graphics corruption in some situations when JIT mode is direct and using emulated RTG boards. Only uaegfx is always fully JIT direct compatible.
- JIT MOVEM.x ,-(An) and includes An: use MOVEM indirect safe mode. Tester does not complain anymore.
- PCem RTG board 15 and 16-bit lores modes did not horizontally double correctly.
- HBSTRT very near end of scanline was detected as missed, opening left border.
- Programmed HBLANK end mid screen + bitplanes active (=totally broken situation) caused random graphics corruption.
- ECS Denise horizontal blanking logic updated, it is quite complex and previous was not complete. Note that in real world it can only work if display uses H/V sync (not composite sync) = VGA monitor. CSYNC vs HSYNC/VSYNC "monitor cable" option will be added later.
- Programmed Denise/Lisa side vertical blank ended 1 line too early. It takes 1 more line before Denise/Lisa ends it.
- Programmed vertical blank generated blank scanline was not always drawn fully to end of scanline.
Other updates and earlier version bug fixes:
- If warp mode and non-qualifier key is pressed: send release event immediately. It is now possible to type normally in warp mode. Note that physical key release will generate another, almost always harmless, key release event.
- PCem Cirrus Logic SVGA emulation planar support enabled. Picasso96 supports 4bit/16 color planar mode.
- Hardware emulated RTG mode + horizontal or vertical doubling + magic mouse: mouse position calculation incorrectly used doubled coordinates.
- Only process mouse/keyboad input Windows events during mid frame (used to reduce input lag) and process other events during vblank.